An example of an integral type Analog/Digital (AD) converter used in a Complementary Metal Oxide Semiconductor (CMOS) image sensor, etc. is a single slope type AD converter. The single slope type AD converter compares an analog input voltage and a reference voltage having a ramp waveform linearly changed according to a time using a comparator, counts a time until an output of the comparator is inverted using a counter circuit, and outputs the counted result as a digital value.
An example of a technology of further speeding up the AD converter or further improving a precision of the AD converter is a technology of performing AD conversion by measuring a time when the output of the comparator is inverted in more detail using a Time to Digital Converter (TDC) and outputting the measured time together with the output of the counter.
For example, an integral type AD converter 101 disclosed in Non Patent Literature 1 includes a comparator 10, a counter 30, a TDC 140 and a Delay Locked Loop (DLL) 50 as illustrated in FIG. 11. An operation of the integral type AD converter 101 will be described with reference to FIG. 12. In the integral type AD converter 101, the comparator 10 compares an analog signal yin with a reference signal ramp having a ramp waveform linearly changed according to a time and outputs the compared result as an output voltage vcomp. As illustrated in FIG. 12A, the reference signal ramp is linearly changed according to a passing of time, and a magnitude relation between the analog input signal yin and the reference signal ramp is reversed at a time point tinv. An output vcomp of the comparator 10 is inverted at the time point tinv. The counter 30 counts a time up to the time point tinv based on a reference clock signal which is input, and outputs the counted result as an output result out2.
FIG. 12(b) illustrates a portion obtained by enlarging a portion around a time point tinv of FIG. 12(a). The TDC 140 measures a time period t within a period T corresponding to a reference clock, which is configured from a starting time point of the period T to the time point tinv, and outputs the measured result as an output result out1. A detailed measuring method will be described with reference to FIG. 13. The DLL 50 outputs four clock signals CLKA, CLKB, CLKC and CLKD having the same frequency as that of a reference clock signal, and having different phases each of which is changed by 45 degrees. The TDC 140 latches values of the four clock signals CLKA, CLKB, CLKC and CLKD at the time point tinv when the output of the comparator 10 is inverted. For example, in FIG. 13, a magnitude relation between the analog input signal yin and the reference signal ramp is reversed at the time point tinv, and the output vcomp of the comparator 10 is inverted. At this time, the clock signal CLKA is in a high level zone, the clock signals CLKB, CLKC and CLKD are in a low level zone, and the values of the clock signals CLKA, CLKB, CLKC and CLKD are latched. As described above, the TDC 140 measures a time of the time point tinv within one clock period in a time unit more minutely than the one clock period, using phase information indicating whether each of the clock signals CLKA, CLKB, CLKC and CLKD is in the high level zone or in the low level zone.
Further, an AD converter disclosed in Patent Literature 1 also includes the comparator 10, the counter 30, and the TDC 140, and performs the same processing as that of the integral type AD converter 101 disclosed in Non-Patent Literature 1.